Products - Sinetec Technologies
Oscilloscpe,Analyzers,meters -M8000 Series
Product Description
M8020A J-BERT High-Performance BERT Configuration for Bench-Top 5-Slot Chassis
The high-performance Agilent J-BERT M8020A enables fast, accurate receiver characterization of single- and multi-lane devices running up to 16 or 32 Gb/s.With todays highest level of integration, the M8020A streamlines your test setup. In addition, automated in situ calibration of signal conditions ensures accurate and repeatable measurements. And, through interactive link training, it can behave like your DUTs link partner. All in all, the J-BERT M8020A will accelerate insight into your design.
M8048A ISI Channels
The M8048A ISI Channels can be used to emulate channel loses in receiver test setups. A choice of 8 PC board traces with different lengths can be inserted into the signal path. The 8 trace lengths range from 7.7 inch (196 mm) to 34.4 inch (874 mm). By cascading the traces within one box or with the other box a wide range of channels can be emulated with very fine resolution steps. With their small size the ISI channels can be located closely to the device under test. The cascadable ISI channels are complemented by Agilents compliance channels for SATA, DisplayPort, PCI Express, and HDMI.
M8061A Multiplexer 2:1 With De-Emphasis 28 Gb/s
R&D and test engineers who need to characterize serial interfaces of up to 28.4 Gb/s can use the M8061A 2:1 Multiplexer with optional de-emphasis to extend the rate of J-BERT N4903B pattern generator. For the most accurate receiver characterization results, the M8061A provides four calibrated de-emphasis taps, which can be extended to eight taps, built-in superposition of level interference and Clock/2 jitter injection. The M8061A is a 2-slot AXIe module that can be controlled via USB from J-BERTs user interface. Application examples for M8061A: Optical transceivers such as 100GBASE-LR4, -SR4 and -ER4, 32G Fibre Channel SERDES and chip-to-chip interfaces, such as OIF CEI Backplanes, cables, such as 100GBASE-KR4, -CR4 Next generation computer buses, such as PCI Express ® 4 Emulate transmitter de-emphasis with up to 8 taps Many multi gigabit serial interfaces use transmitter de-emphasis to compensate for electrical signal degradations caused by printed circuit boards or cables between the transmitter and the receiver ports. R&D and test engineers who need to characterize receiver ports under realistic and worst case conditions require a pattern generator that allows to accurately emulate transmitter de-emphasis with adjustable multi-tap de-emphasis levels. The M8061A can be used in combination with J-BERT N4903B as shown below.