Products - Sinetec Technologies
Oscilloscpe,Analyzers,meters -Accessories and supplementary products for BERTs a
Product Description
M8061A Multiplexer 2:1 With De-Emphasis 28 Gb/s
R&D and test engineers who need to characterize serial interfaces of up to 28.4 Gb/s can use the M8061A 2:1 Multiplexer with optional de-emphasis to extend the rate of J-BERT N4903B pattern generator. For the most accurate receiver characterization results, the M8061A provides four calibrated de-emphasis taps, which can be extended to eight taps, built-in superposition of level interference and Clock/2 jitter injection. The M8061A is a 2-slot AXIe module that can be controlled via USB from J-BERT’s user interface. Application examples for M8061A: Optical transceivers such as 100GBASE-LR4, -SR4 and -ER4, 32G Fibre Channel SERDES and chip-to-chip interfaces, such as OIF CEI Backplanes, cables, such as 100GBASE-KR4, -CR4 Next generation computer buses, such as PCI Express ® 4 Emulate transmitter de-emphasis with up to 8 taps Many multi gigabit serial interfaces use transmitter de-emphasis to compensate for electrical signal degradations caused by printed circuit boards or cables between the transmitter and the receiver ports. R&D and test engineers who need to characterize receiver ports under realistic and worst case conditions require a pattern generator that allows to accurately emulate transmitter de-emphasis with adjustable multi-tap de-emphasis levels. The M8061A can be used in combination with J-BERT N4903B as shown below.
N4880A Reference Clock Multiplier
Description Accurate and simplified receiver testing for PCI Express, MIPI M-PHY and SD UHS-II The N4880A reference clock multiplier fills a critical requirement for R&D and test engineers who need to characterize and release the next generation of PCI Express main boards, MIPI M-PHY chipsets and SD card UHS-II host devices. With its support for multiple reference-clock rates, the N4880A will help you accurately characterize and verify standards compliance under easy-to-reproduce test conditions. Lock the stressed-pattern generator to a system reference clock In common reference-clock architectures, where the host cannot be driven by an external reference clock its necessary to lock the stressed-pattern generator to the same system reference clock used by the receiver under test. This is because the receiver under test also derives its sampling clock from this reference clock. Locking the stressed pattern generator to the same reference clock as the receiver under test ensures accurate and reproducible jitter-tolerance test results. Get the most precise and reproducible receiver tolerance test results for PCI Express mainboards, MIPI M-PHY and SD UHS-II hosts The N4880A provides a multiplying phase-locked loop (PLL) which enables users to lock the pattern generator of J-BERT N4903B or ParBERT 81250A to a system reference clock. Spread Spectrum Clocking (SSC) and low frequency jitter are fed through the N4880A up to its PLL loop bandwidth of 2 or 5 MHz. The N4880A tolerates huge amounts of SSC for UHS-II reference clocks and offers excellent input sensitivity to handle very low voltage levels. Increase your R&D efficiency with a future-proof investment By using N4880A for receiver test, R&D engineers efficiency is increased as the test complexity is reduced by eliminating complicated and time-consuming work-arounds. The R&D investment is secured by usage for multiple emerging standards. PCI-SIG®, PCIe® and the PCI Express® are US registered trademarks and/or service marks of PCI-SIG. MIPI is a licensed trademark of MIPI, Inc. in the U.S. and other jurisdictions.
N4916B De-emphasis Signal Converter with Optional Clock Multiplier
Description Why is signal de-emphasis needed? The de-emphasis technique is used in the transmission of digital electrical signals at gigabit data rates. De-emphasis is a signal pre-distortion to compensate for signal degradations that occur when transmitting electrical signals with gigabit rates over PC board traces, backplanes, or long cables. With the next generation of serial bus standards operating above 5 Gb/s, sophisticated de-emphasis with multi-tap Finite Impulse Response (FIR) filtering will be needed. Many popular high-speed digital interfaces use de-emphasis, such as PCI Express®, SATA, USB3, QPI, HyperTransport, IEEE 802.3 backplanes (10GBASE-KR, 40GBASE-KR4). What does the N4916B offer? The new N4916B de-emphasis signal converter enables R&D and test engineers to accurately emulate transmitter de-emphasis. The N4916B can emulate transmitter de-emphasis with one pre- and two post-cursors and individually adjustable de-emphasis levels of up to 12.0 dB. With its DC-coupling it tolerates unbalanced pattern streams that often occur in training sequences. The N4916B is designed to be transparent to jitter when stimulated with jitter on data and clock signal, enabling emulation of real-world de-emphasis and jitter conditions that a receiver is expected to tolerate. De-emphasis can also be used to compensate for distortions caused by cables, fixtures or test boards in the test set for more precise device characterization results.
N4963A Clock Synthesizer 13.5 GHz
The N4963A Clock Synthesizer 13.5 GHz generates six pairs of differential square-wave clock outputs from 500 MHz to 13.5 GHz. The instrument features GPIB-programmable output amplitude, DC offset, phase offset, sub-rate trigger, and jitter injection. Applications Extends the operation range of the N4962A Serial BERT Add stressed eye testing to basic BERTs General purpose lab clock source
N4968A Clock and Data Demultiplexer 44 Gb/s
Key Features & Specifications Features Operation from 3.5 to 44 Gb/s Demux-by-2 or demux-by-4 Integrated phase shifter for high-speed clock and data alignment Differential or single-ended input Adjustable sub-rate clock output Description The Agilent Technologies N4968A clock and data demultiplexer 44 Gb/s is a small high-performance 3.5 to 44 Gb/s clock and data demultiplexer, designed to simplify the process of making high-bitrate BER measurements at half- or quarter-rate speeds. The N4968A clock and data demultiplexer 44 Gb/s is capable of operating in demux-by-2 (17 to 8.5 Gb/s) or demux-by-4 (38 to 9.5 Gb/s) modes, with an adjustable sub-rate clock output for triggering BER testers, oscilloscopes, logic analyzers, or other instruments. Applications OC-768/STM-256 100G Ethernet (4 x 25.78 Gb/s) High bit rate research
N4983A Multiplexer and Demultiplexer
Key Features & Specifications Features N4983A-M40 4:1 multiplexer operating from 2 to 44 Gb/s N4983A-D40 1:4 demultiplexer operating from 2.6 to 44 Gb/s Low power consumption Low output jitter Precision connectors (2.92 mm) Description The Agilent Technologies N4983A-M40 broadband 4 to 1 multiplexer operates from 2 to 44 Gb/s. The four quarter-rate inputs are single-ended and AC-coupled, while the full-rate data output is fully differential and DC-coupled. The N4983A multiplexer accepts a half-rate input clock and returns a quarter-rate output clock for driving other circuits. A clock crossing point adjustment pin allows correction for duty cycle distortion. Power supply bias of negative 3.6 V is required. The Agilent Technologies N4983A-D40 broadband 1 to 4 demultiplexer operates from 2.6 to 44 Gb/s. Differential data inputs are DC-coupled and terminated to ground with 50 ohm resistors to minimize reflections. The single-ended, half-rate clock input is AC-coupled and operates with low input power. The N4983A demultiplexer features single-ended AC-coupled outputs with ECL compatible signal levels. Applications OC-768/STM-256, 100G Ethernet (4 x 25.78 Gb/s) High bit rate research
N4984A Clock Divider
Key Features & Specifications Features N4984A-020 operates from 0.2 to 20 GHz N4984A-040 operates from 0.2 to 40 GHz Divide by 1/2/4/8 (N4984A-020) Divide by 2/4/8 (N4984A-040) High input sensitivity Low output jitter Description The Agilent Technologies N4984A Clock Divider units are general purpose test accessories designed for microwave communications and test applications. These accessories provide divide-by-2, divide-by-4, or divide-by-8 output. Inputs and outputs are AC-coupled. The dividers are self-contained and plug into standard AC power sources. Applications Extends trigger range of high speed sampling oscilloscopes Generate synchronized high frequency clock signals Precision timebase measurements